Ultra low stress and low temperature patternable silicone materials for applications within microelectronics

Microelectronic Engineering

Volumn 76, Issue 1-4, 2004, Pages 212-218

  Meynen, H ^a   Bulcke, M Vanden ^b   Gonzalez, M ^b   Harkness, B ^c   Gardner, G ^c   Sudbury Holtschlag, J ^c   Vandevelde, B ^b   Winters, C ^b   Beyne, E ^b  

^a Dow Corning SA Belgium   (Belgium)

^b IMEC   (Belgium)

^c DOW CORNING CORPORATION   (United States)

Author keywords

Low stress; Low temperature; Packaging; Patternable silicones; WL 3010 and WL 5150

Indexed keywords

DIELECTRIC MATERIALS; ELECTRONICS PACKAGING; LOW TEMPERATURE EFFECTS; SILICONES; SOLDERED JOINTS; STRESSES;

LOW STRESS; LOW TEMPERATURE PATTERNABLE SILICONE MATERIALS; WL-3010; WL-5150;

MICROELECTRONICS;

EID: 4544236365     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2004.07.002     Document Type: Conference Paper

References (5)

1. T. Matsuda, M.J. Shapiro, S.V. Nguygen, Dual Frequency plasma CVD fluorsilicate glass deposition for 0.25 μm inlerlevel dielectric, in: Proceedings of First International Dielectrics for VLSI/ULSI Multilevel Interconnection Conference (DUMIC), 1995, p. 22-28.
2. B.R. Harkness, G.B. Gardner, J.S. Alger, M.R. Cummings, J.L. Princing, Y. Lee, H.Meynen, M. Gonzalez, B. Vande-velde, C. Witters, E. Beyne, Photopatternable silicone compositions for electronics packaging applications, Proceedings of SPIE-The International Society for Optical Engineering (2004) 5376, (Pt. 1. Advances in Resist Technology and Processing XXI), p. 517-524.
3. M. Gonzalez, B. Vandevelde, C. Winters, E. Beyne, Y.J. Lee, L. Larson, B.R. harkness, M. Mohamed, H. Meynen, E. Vanlathem, An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration, in: Proceedings of the 53rd Electronic Components and Technology Conference, 2003, pp. 857-863.
4. H. Hedler,T. Meyer, W. Leiberg, R. Irsigler, Elastic bump wafer level packaging platform (not only) for memory products, IMAPS 2003.
5. G.B. Gardner, B.R. Harkness, E. Ohare, H. Meynen, M. Vanden Bulcke, M. Gonzalez, E. Beyne, Integration of a low stress patternable silicone into a wafer level package, in: Proceedings of the 54th Electronic Components and Technology Conference, 2004, to be published.