A low-power switched-current CDMA matched filter with on-chip V-I and I-V converters

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 214-217

  Yamasaki, Toshihiko ^a   Nakayama, Tomoyuki ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CODE DIVISION MULTIPLE ACCESS; CORRELATION METHODS; ELECTRIC CONVERTERS; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS; SYNCHRONIZATION; TECHNOLOGY;

ACTIVATION FLAG; CELL ARRAYS; CHIP AREA; SWITCH CONTROL;

ELECTRIC FILTERS;

EID: 4544226087     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. J. Wu, M. Liou, H. Ma and T. Chiueh, "A 2.6V, 44-MHz all digital QPSK direct-sequence spread spectrum transceiver IC," IEEE JSSC, vol. 32, pp. 1499-1510, Oct. 1997.
2. T. Yamada, S. Goto, N. Takayakma, Y. Matsushita, Y. Harada, and H. Yasuura, "Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems," IEICE Trans. Elec., vol. E86-C, no. 1, pp. 79-88, Jan. 2003.
3. E. Nishimori, C. Kimura, A. Nakagawa, and K. Tsubouchi, "CCD matched filter in spread spectrum communication," Proc. IEEE Int. Symp. on Personal, Indoor and Mobile Radio Communications, vol. 1, pp. 396-400, Sep. 1998.
4. H. Nakase, T. Kasai, Y. Nakamura, K. Masu, and K. Tsubouchi, "One chip demodulator using RF front-end SAW correlator for 2.4GHz asynchronous spread spectrum modem," The fifth IEEE Symp. Personal, Indoor and Mobile Radio Communications, pp. 374-378, 1994.
5. D. Senderowicz, S. Azuma, H, Matsui, K. Kara, S. Kawama, Y. Ohta, M. Miyamoto, and K. Iizuka, "A 23-mW 256-Tap 8Msample/s QPSK Matched Filter for DS-CDMA Cellular Telephony Using Recycling Integrator Correlators," IEEE Int. Solid-State Circuit Conference, pp. 354-355, Feb. 2000.
6. M. Sakai, T. Sakai, and T. Matsumoto, "A Low Power Matched Filter for DS-CDMA Based on Analog Signal Processing," IEICE Trans. Fund., vol. E86-A, no. 4, pp. 752-757, Apr. 2003.
7. T. Yamasaki, T. Fukuda, and T. Shibata, "A Floating-Gate-MOS-Based Low-Power CDMA Matched Filter Employing Capacitance Disconnection Technique," VLSI Circuits Dig. Tech. Papers, pp. 267-270, 2003.
8. K. Togura, H. Nakase, K. Kubota, K. Masu, and K. Tsubouchi, "Low Power Current-Cut Switched-Current Matched Filter for CDMA," IEICE Trans. Elec., vol. E84-C, no. 2, pp. 212-219, Feb. 2001.
9. T. Shitaba and T. Ohmi, "A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations," IEEE Trans. ED, vol. 39, no. 6, pp. 1444-1455, 1992.
10. M. Hamada, T. Terazawa, T. Higashi, S. Kitabayashi, S. Mita, Y. Watanabe, M. Ashino, H. Hara, and T. Kuroda, "Flip-Flop Selection Technique for Power-Delay Trade-off," IEEE Int. Solid-State Circuit Conf., vol. XLII, pp. 270-271, Feb. 1999.