Vertical floating-gate 4.5F2 split-gate NOR flash memory at 110nm node

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 72-73

  Lee, Dana ^a   Tsui, Felix ^a   Yang, Jeng Wei ^a   Gao, Feng ^a   Lu, Wen Juei ^a   Lee, Yeeheng ^a   Chen, Chi Tsai ^a   Huang, Vincent ^b   Wang, Pin Yao ^b   Liu, M H ^b   Hsu, H C ^b   Chang, Simon ^b   Chang, S Y ^b   Van Tran, Hieu ^a   Frayer, Jack ^a   Hu, Yaw Wen ^a   Yeh, Bing ^a   Chen, Bomy ^a  

^a SILICON STORAGE TECHNOLOGY INC   (United States)

^b POWERCHIP TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

Flash memory; Self aligned; Vertical channel

Indexed keywords

APPROXIMATION THEORY; BALLISTICS; COMPUTER SIMULATION; ELECTRIC FIELDS; LITHOGRAPHY; MOSFET DEVICES; POLYSILICON; THRESHOLD VOLTAGE; TRANSISTORS;

FLOATING-GATE (FG) CHANNELS; SELF-ALIGNED; SUBSTRATE HOT ELECTRON INJECTION (SHEI); VERTICAL-CHANNELS;

FLASH MEMORY;

EID: 4544224758     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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