A step towards a better understanding of silicon passivated (100)Ge p-channel devices

ECS Transactions

Volumn 6, Issue 1, 2007, Pages 53-63

  Pourtois, G ^a   Houssa, M ^a,b   De Jaeger, B ^a   Leys, F E ^a   Kaczer, B ^a   Martens, K ^a,b   Caymax, M ^a   Meuris, M ^a   Groeseneken, G ^a,b   Heyns, M M ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ENERGY GAP; GERMANIUM; INTERFACE STATES; LOGIC GATES; SILICON; SUBSTRATES; THRESHOLD VOLTAGE; WORK FUNCTION;

CAPACITANCE VOLTAGE CHARACTERISTIC; ELECTRONIC GAP; FIRST-PRINCIPLES CALCULATION; FLAT-BAND VOLTAGE; GERMANIUM SURFACE; INTERFACE DIPOLE; P CHANNEL DEVICE; POSITIVE VALUE;

PASSIVATION;

EID: 45249107658     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2727387     Document Type: Conference Paper

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