A 10b 205MS/S 1mm2 90nm CMOS pipeline ADC for flat-panel display applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 458-460

  Lee, Seung Chul ^a   Jeon, Young Deuk ^a   Kim, Kwi Dong ^a   Kwon, Jong Kee ^a   Kim, Jongdae ^a   Moon, Jeong Woong ^b   Lee, Wooyol ^b  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b LG Electronics Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; FLAT PANEL DISPLAYS; VOLTAGE CONTROL;

CMOS PROCESSES; CORE ADC POWER CONSUMPTION; LDO REGULATORS;

POWER CONVERTERS;

EID: 34548848838     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373492     Document Type: Conference Paper

References (4)

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2. S.-C. Lee, K.-D. Kim, J.-K. Kwon, et al., "A 10-bit 400-MS/s 160-mW 0.13mm CMOS Dual-Channel Pipeline ADC Without Channel Mismatch Calibration," IEEE J. Solid-State Circuits, vol. 41, pp. 1596-1605, Jul., 2006.
3. K. Gulari, H. S. Lee, "A High-Swing CMOS Telescopic Operational Amplifier," IEEE J. Solid-State Circuits, vol. 33, pp. 2010-2019, Dec., 1998.
4. R. Eschauzier, J. Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers, Boston, MA: Kluwer Academic, 1995.