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Volumn , Issue , 2007, Pages 159-162
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A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold
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Author keywords
[No Author keywords available]
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Indexed keywords
ANALOG TO DIGITAL CONVERSION;
ARCHITECTURAL DESIGN;
EMBEDDED SYSTEMS;
MULTICARRIER MODULATION;
EUROPEAN;
FRONT END;
HIGH BANDWIDTH;
MEAS URED RESULTS;
PIPELINED ADC;
POWER ON;
POWER SAVINGS;
POWER SCALEABLE;
SAMPLE-AND-HOLD (SHA);
SETTLING BEHAVIOR;
SOLID-STATE CIRCUITS CONFERENCE;
ENERGY CONSERVATION;
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EID: 44849098987
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ESSCIRC.2007.4430270 Document Type: Conference Paper |
Times cited : (4)
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References (7)
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