Correlation between break-in characteristics and pad surface conditions in silicon wafer polishing

Journal of Materials Processing Technology

Volumn 205, Issue 1-3, 2008, Pages 360-365

  Park, Kihyun ^a   Park, Jaehong ^b   Park, Boumyoung ^a   Jeong, Haedo ^a  

^a Pusan National University   (South Korea)

^b Nitta Haas Inc   (Japan)

Author keywords

Break in delay; Break in time; Buffing process; Pad; Surface roughness

Indexed keywords

CORRELATION METHODS; POLISHING; SURFACE ROUGHNESS;

BREAK-IN DELAY; BREAK-IN TIME; BUFFING PROCESS;

SILICON WAFERS;

EID: 44749094404     PISSN: 09240136     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jmatprotec.2007.11.203     Document Type: Article

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