Photo-battery fabricated in silicon on sapphire CMOS

Electronics Letters

Volumn 44, Issue 12, 2008, Pages 766-767

  Marwick, M A ^a   Andreou, A G ^a  

^a Johns Hopkins University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; COMPUTER NETWORKS; MICROFLUIDICS; NONMETALS; OPTICS; SAPPHIRE; SILICON; TECHNOLOGY;

BACKSIDE ILLUMINATION; CHARACTERISATION; ENERGY HARVESTING; INFRARED (IR); OPTICAL TRANSPARENCY; OUTPUT VOLTAGES; SAPPHIRE SUBSTRATES; SILICON AREA; SILICON-ON-SAPPHIRE (SOS) CMOS; ULTRAVIOLET (UV);

SILICON ON SAPPHIRE TECHNOLOGY;

EID: 44649155254     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20080374     Document Type: Article

References (5)

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3. Dubbelday, W., Flesner, L., Garcia, G., Imthurm, G., and Hirschi, R.: ' Very high voltage SOS photocell array ', IEEE SOI Conf. Proc., Vail Valley, CO, USA, 1991, p. 84-85
4. Bellew, C., Hollar, S., and Pister, K.: ' An SOI process for fabrication of solar cells, transistors and electrostatic actuators ', Int. Conf. on Solid State Sensors, Actuators and Microsystems, Boston, MA, USA, June, 2003, p. 1075-1079
5. Marwick, M.A., Tejada, F., Pouliquen, P., and Andreou, A.: ' Dark current and noise of 100 nm thick silicon on sapphire CMOS lateral PIN photodiodes ', Proc. Int. Symp. on Circuits and Systems, Kos, Greece, May, 2006