Property-specific testbench generation for guided simulation

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 524-531

  Gupta, A ^a   Casavant, A E ^a   Ashar, P ^a   Liu, X G ^b   Mukaiyama, A ^c   Wakabayashi, K ^c  

^a NEC LABORATORIES AMERICA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER AIDED DESIGN; FORMAL LOGIC; ITERATIVE METHODS; MODEL CHECKING; TREES (MATHEMATICS);

ABSTRACT MODELING; COMPUTATION TREE LOGIC; COMPUTING RESOURCE; CORRECTNESS PROPERTIES; COVERAGE METRICS; FUNCTIONAL VALIDATION; PRACTICAL ISSUES; SYMBOLIC MODEL CHECKING;

DESIGN;

EID: 4444345133     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994973     Document Type: Conference Paper

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