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Volumn , Issue , 2004, Pages 673-677

A dual-core 64b UltraSPARC microprocessor for dense server applications

Author keywords

Cache; Coupling noise; Deep submicron technology; Dense server; Dual core; L2; Leakage; Multiprocessor; NBTI; Negative Bias Temperature Instability; Throughput computing; UltraSPARC

Indexed keywords

AMPLIFIERS (ELECTRONIC); ATTENUATION; BUFFER STORAGE; INTEGRATED CIRCUIT LAYOUT; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; SPURIOUS SIGNAL NOISE; STANDARDS;

EID: 4444289720     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996750     Document Type: Conference Paper
Times cited : (4)

References (10)
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  • 2
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  • 3
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    • A dual-core 64b UltraSPARC microprocessor for dense server applications
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    • T. Takayanagi et al., "A Dual-Core 64b UltraSPARC Microprocessor for Dense Server Applications," ISSCC Dig. Tech. Papers, Feb. 2004, pp. 58-59
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    • Takayanagi, T.1
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    • Lev, L. A., et al, "A 64b microprocessor with multimedia support," IEEE J. Solid State Circuits, vol. 30, no. 11, Nov. 1995. pp. 1227-1238
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  • 5
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    • G. K. Konstadinidis et al., "Implementation of a ThirdGeneration 1.1-GHz 64-bit Microprocessor," IEEE J. Solid State Circuits, vol. 37, no. 11, Nov. 2002
    • (2002) IEEE J. Solid State Circuits , vol.37 , Issue.11
    • Konstadinidis, G.K.1
  • 6
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    • A 64-entry 167MHz fully-associative TLB for a RISC microprocessor
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  • 7
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    • E. Seevink et al., "Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's," IEEE J. Solid State Circuits, vol. 26, no.4, April 1991, pp. 525-536
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  • 8
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    • N. Shibata, "Current Sense Amplifiers for Low-Voltage Memories", IEICE Trans. Electron., vol. E79-C, no. 8, pp. 1120-30, Aug. 1996.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.