A dual-core 64b UltraSPARC microprocessor for dense server applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Takayanagi, Toshinari ^a   Shin, Jinuk Luke ^a   Petrick, Bruce ^a   Su, Jeffrey ^a   Levy, Howard ^a   Pham, Ha ^a   Son, Jin ^a   Moon, Nathan ^a   Bistry, Dina ^a   Singh, Mandeep ^a   Mathur, Vikas ^a   Leon, Ana Sonia ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY CONTROLLERS; NETWORK COMPUTING; VOLTAGE DROP;

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; DIELECTRIC MATERIALS; ERROR CORRECTION; GATES (TRANSISTOR); INTERFACES (COMPUTER); LEAKAGE CURRENTS; SERVERS; SPURIOUS SIGNAL NOISE;

MICROPROCESSOR CHIPS;

EID: 20244379233     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S. Kapil, "Gemini: A Power-efficient Chip Multi-Threaded UltraSPARC Processor," 15th Hot Chips Symp., Aug. 2003
2. L. A. Lev et al, "A 64b Microprocessor with Multimedia Support," IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1227-1238, Nov. 1995.
3. E. Anderson, "A 64-Entry 167MHz Fully-Associative TLB for a RISC Microprocessor," ISSCC Dig. Tech. Papers, pp. 260-261, Feb. 1996.
4. V. Reddy et al., "Impact of Negative Bias Temperature Instability of Digital Circuit Reliability," Reliability Physics Symp., pp. 248-254, 2002.