Reconfigurable FLUX networks

Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Volumn , Issue , 2006, Pages 81-88

  Vassiliadis, Stamatis ^a   Sourdis, Ioannis ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECTION NETWORKS; PARALLEL PROCESSING SYSTEMS; PATTERN RECOGNITION; TELECOMMUNICATION TRAFFIC;

SYNTHETIC BENCHMARKS; TRAFFIC LOADS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 43749113376     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2006.270298     Document Type: Conference Paper

References (15)

1. S. Vassiliadis, L. A. Sousa, and G. N. Gaydadjiev, "The Midlifekicker Microarchitecture Evaluation Metric," in Proceedings of the IEEE Int. Conf. ASAP05, July 2005, pp. 92-97.
2. W. Bouknight, S. Desenberg, D. McIntyre, J. Randall, A. Sameh, and D. Slotnick, "The Illiac IV system," Proc. IEEE, vol. 60, April 1972.
3. I. Lee and D. Smitley, "A Synthesis Algorithm for Reconfigurable Interconnection Networks," IEEE Trans. Computers, vol. 37, no. 6, pp. 691-699, 1988.
4. F. T. Leighton, Introduction to parallel algorithms and architectures: array, trees, hypercubes. CA, USA: Morgan Kaufmann Inc., 1992.
5. S. Ranka and S. Sahni, Hypercube Algorithms for Image Processing and Pattern Recognition. New York City, NY: Springer-Verlag, 1990.
6. M. Reingold, J. Nievergelt, and N. Deo, Combinational Algorithms: Theory and Practice. New Jersey: Prentice-Hall, Inc., 1977.
7. B. Manien and I. Sudborough, "Embedding one interconnection network in another," In Computational Graph Theory, G. Tinhofer et al. Eds., Computing Supplementa, vol. 7, pp. 257-282, 1990.
8. L. Snyder, "Introduction to the Configurable, Highly Parallel Computer." IEEE Computer, vol. 15, no. 1, pp. 47-56, 1982.
9. S. Vassiliadis and I. Sourdis, "FLUX Networks: Interconnects on Demand," in Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS), July 2006, pp. 160-167.
10. S. Vassiliadis and I. Sourdis, "Reconfigurable Fabric Interconnects," in International Symposium on System-on-Chip (SoC), November 2006.
11. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K. Bertels, G. Kuzmanov, and E. M. Panainte, "The Molen Polymorphic Processor," IEEE Transactions on Computers, pp. 1363-1375, November 2004.
12. P. Sedcole, B. Blodget, J. Anderson, P. Lysaght, and T. Becker, "Modular Partial Reconfiguration in Virtex FPGAs," in Proceedings of 15th Int. Conference on Field Programmable Logic and Applications, 2005.
13. L. M. Ni and P. K. McKinley, "A survey of wormhole routing techniques in direct networks," Computer, vol. 26, no. 2, pp. 62-76, 1993.
14. S.-K. Lee and H.-A. Choi, "Embedding of Complete Binary Trees into Meshes with Row-Column Routing," IEEE Trans. Parallel Distrib. Syst., vol. 7, no. 5, pp. 493-497, 1996.
15. Xilinx, "Virtex-II pro Platform FPGA Handbook."