Noise and linearity analysis for a 1.9 GHz CMOS LNA

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn 2, Issue , 2002, Pages 409-414

  Guo, Wei ^a   Huang, Daquan ^a  

^a ZHEJIANG UNIVERSITY   (China)

Author keywords

Circuit simulation; Computational modeling; Computer architecture; Computer simulation; Integrated circuit noise; Linearity; Low noise amplifiers; MOSFET circuits; Radiofrequency amplifiers; Radiofrequency integrated circuits

Indexed keywords

ANALOG CIRCUITS; CIRCUIT SIMULATION; COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUITS; MOSFET DEVICES; RADIO FREQUENCY AMPLIFIERS;

COMPUTATIONAL MODEL; INTEGRATED CIRCUIT NOISE; LINEARITY; MOSFET CIRCUITS; RADIO FREQUENCY INTEGRATED CIRCUITS;

LOW NOISE AMPLIFIERS;

EID: 43549100828     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2002.1115281     Document Type: Conference Paper

References (6)

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2. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge Univ. Press, 1998.
3. Piljae Park, et al, "Linearity, Noise Optimization for Two Stage RF CMOS LNA", Proc. Of IEEE, Volume: 2, 2001, pp. 756-758.
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5. Wei Jin, et al, "Noise Modeling and Characterization for 1.5-V 1.8-GHz SOI Low-Noise Amplifier", IEEE Transaction on Electron Devices, Volume: 48, No. 4, April 2001, pp. 803-809.
6. A. Van der Ziel, Noise in Solid State Devices and Circuits, New York: Wiley, 1986.