Oscillatorless clock multiplication

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 630-633

  Aguiar, Rui L ^a   Santos, Diizis M ^a  

^a UNIVERSITY OF AVEIRO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

CUSTOM CIRCUITS; DUTY-CYCLE; INTEGER FACTORS; LOCAL OSCILLATORS; OSCILLATOR SYSTEMS; SYSTEM SUPPORTS;

HYBRID SYSTEMS;

CLOCKS;

EID: 4344717741     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922316     Document Type: Conference Paper

References (9)

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2. Alvarez, J., Sanchez, H., Gerosa, G and Countryman, R., "A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors", IEEE Journal of Solid-State Circuits, vol. 30, n. 4, Apr 1995.
3. Rabaey, J., Digital Integrated Circuits. Prentice-Hall, 1996.
4. Rusu, S and Tarn, S., "Clock Generation and Distribution for the First IA-64 Microprocessor", IEEE Intl. Solid-State Conf. ISSCC'OO. Feb. 2000.
5. Aguiar, R.L and Santos, D.M., "Clock Distribution Strategy for IP-Based Development" in VLSI: Systems in a Chip, Silveira, L.M. Devadas, S and Reis. R. (eds.). Chapman & Hill, 1999.
6. Friedman, E., "Introduction-Clock Distribution Networks in VLSI Circuits and Systems", Editor paper in the IEEE reprint Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press, 1995.
7. Kim, B., Weingandt T" and Gray, P., "PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design", 1SCAS'94, IEEE International Symposium on Circuits and Systems, Jun. 94.
8. Yuan, M.-S and Wang, C.-K., "PLL Circuits" in The VLSI Handbook, Chen, W.-K. (ed.), IEEE Press, 2000.
9. Vasconcelos. E. Aguiar. R.L., and Santos, D., "A 0.8 pm CMOS, 622 Mb/s SDH/SONET Communication System," MWSCAS'99, 42nd Midwest Symposium on Circuits and Systems, Las Cruces, New Mexico, Aug 1999, pp.843-846.