0.8 μm CMOS, 622 Mb/s SDH/SONET communication system

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1999, Pages 232-235

  de Vasconcelos, Eduardo ^a   Aguiar, Rui L ^a   Santos, Dinis M ^a  

^a UNIVERSITY OF AVEIRO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; DIGITAL COMMUNICATION SYSTEMS; EMITTER COUPLED LOGIC CIRCUITS; FIBER OPTIC NETWORKS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTICAL FIBERS; PHASE LOCKED LOOPS; SIGNAL RECEIVERS;

DELAY LOCKED LOOPS; DIGITAL PHASE LOCKED LOOPS;

CMOS INTEGRATED CIRCUITS;

EID: 0033292772     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)