Towards evolvable IP cores for FPGAs

Proceedings - NASA/DoD Conference on Evolvable Hardware, EH

Volumn 2003-January, Issue , 2003, Pages 145-154

  Sekanina, L ^a  

^a BRNO UNIVERSITY OF TECHNOLOGY   (Czech Republic)

Author keywords

Adaptive arrays; Application software; Circuit synthesis; Design methodology; Field programmable gate arrays; Genetics; Hardware; Information technology; Libraries; Paper technology

Indexed keywords

APPLICATION PROGRAMS; COMPUTER HARDWARE; HARDWARE; INFORMATION TECHNOLOGY; LIBRARIES; LOGIC GATES; LOGIC SYNTHESIS; NASA; RECONFIGURABLE HARDWARE;

ADAPTIVE ARRAYS; CIRCUIT SYNTHESIS; DESIGN METHODOLOGY; GENETICS; PAPER TECHNOLOGY;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 4344710814     PISSN: 15506029     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EH.2003.1217659     Document Type: Conference Paper

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