High-speed and wide-tuning-range LC frequency dividers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2004, Pages

  Yamamoto, Ken ^a   Norimatsu, Takayasu ^a   Fujishima, Minoru ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; ENERGY UTILIZATION; NATURAL FREQUENCIES; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; VOLTAGE CONTROL; WIRELESS TELECOMMUNICATION SYSTEMS;

BLOCK DIAGRAMS; POWER CONSUMPTION; SELF-OSCILLATING FREQUENCIES; WIRELESS COMMUNICATIONS;

FREQUENCY DIVIDING CIRCUITS;

EID: 4344709571     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. H. Wu and A. Hajimiri, "A 19GHz 0.5mW 0.35μm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement," ISSCC Digest of Tech. Papers, pp. 412-413, Feb. 2001.
2. R. Betancourt-Zamora, S. Verma and T. Lee, "1GHz and 2.8GHz CMOS Injection-locked Ring Oscillator Prescalers," VLSI Symposium, pp. 47-50, June 2001.
3. J. Wong, V. Cheung and H. Luong, "A 1V 2.5mW 5.2GHz Frequency Divider in a 0.35μm CMOS Process", VLSI Symposium, pp. 190-193, June 2002.
4. J. Lee and B. Razavi, "A 40-GHz Frequency Divider in 0.18-μm CMOS Technology," VLSI Symposium, pp. 259-262, June 2003.
5. H. R. Rategh, H. Samavari and T. H. Lee, "A CMOS Frequency Synthesizer with Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver," IEEE Journal of Solid-State Circuits, vol. 35, pp. 780-787, May 2000.
6. K. Yamamoto, T. Norimatsu and M. Fujishima, "1 V 2 GHz CMOS Frequency Divider" IEE Electronics Letters, vol. 39, pp. 1227-1228, Aug. 2003.