A cascaded continuous-time σΔ modulator with 80 DB dynamic range

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Ortmanns, Maurits ^a   Kuderer, Markus ^a   Manoli, Yiannos ^a   Gerfers, Friedel ^b  

^a UNIVERSITY OF FREIBURG   (Germany)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CASCADE CONNECTIONS; DIGITAL SIGNAL PROCESSING; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; MULTIPLEXING EQUIPMENT; NETWORKS (CIRCUITS); RESISTORS; SIGNAL NOISE MEASUREMENT;

CT CIRCUITS; DIGITAL NOISE; DYNAMIC RANGE; HIGH RESOLUTION CIRCUITS;

DELTA SIGMA MODULATION;

EID: 4344705429     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Y. Geerts et al., "A high-performance multibit ΣΔ CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1829-1840, Dec. 2000.
2. F. Medeiro et al., "A 13-bit, 2.2-MS/s, 55-mW Multibit Cascade ΣΔ Modulator in CMOS 0.7-μm Single-Poly Technology," IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 748-760, Jun. 1999.
3. O. Shoaei, Continuous-Time ΣΔ A/D Converters for High Speed Applications, Ph.D. thesis, Carleton University, Ottawa, Canada, 1995.
4. M. Ortmanns et al., "On the synthesis of cascaded continuous-time ΣΔ Modulators," ISCAS, pp. 419-422, 2001.
5. M. Ortmanns et al., "Successful Design of cascaded CT ΣΔ Modulators," ICECS, pp. 321-324, 2001.
6. A. Marquez et al., "Optimal parameters for ΔΣ modulators topologies," IEEE Trans. Circuits Syst. II, vol. 45, no. 9, pp. 1232-1241, September 1998.