Delay estimation of SCL gates with output buffer

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2001, Pages 719-722

  Alioto, M ^a   Palumbo, G ^a   Pennisi, S ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY ESTIMATION; DESIGN PHASIS; LOAD CONDITION; OUTPUT BUFFER; PHYSICAL MEANINGS; PROCESS PARAMETERS; PROPAGATION DELAYS;

EID: 4344572617     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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