Modeling propagation delay of MUX, XOR, and D-latch source-coupled logic gates

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2451, Issue , 2002, Pages 429-437

  Alioto, M ^a   Palumbo, G ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; COMPUTER CIRCUITS; DELAY CIRCUITS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES;

CMOS TECHNOLOGY; DELAY MODELING; DELAY VALUES; DOMINANT POLE APPROXIMATION; PROPAGATION DELAYS; SIMULATED RESULTS; SOURCE COUPLED LOGIC GATES; SPECTRE SIMULATIONS;

EMITTER COUPLED LOGIC CIRCUITS;

EID: 23044533316     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45716-x_43     Document Type: Conference Paper

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