B-DTNMOS: A novel bulk dynamic threshold NMOS scheme

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Elgharbawy, Walid ^a   Bayoumi, Magdy ^a  

^a University of Louisiana at Lafayette   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SIGNALS; ENERGY SAVINGS; SUPPLY VOLTAGE; TRANSCONDUCTANCE GAIN;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; LEAKAGE CURRENTS; PROBLEM SOLVING; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

MOSFET DEVICES;

EID: 4344668717     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. Ko, and C. Hu, "Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI," IEEE Trans. Elec. Dev., vol. 44, pp. 414-421, Mar. 1997
2. H. Soeleman, K. Roy, and B. Paul, "Robust Subthreshold Logic for Ultra-Low Power Operation," IEEE Trans. VLSI Systems, vol. 9, no. 1, pp. 90-99, Feb. 2001
3. th Intl Conf. on Microelectronics, 2001, pp. 75-78
4. th Intl Conf. on Microelectronics, 2000, pp. 9-10
5. th Intl Conf. on VLSI Design, 2000, pp. 24-29
6. J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, Prentice-Hall, Second Edition, NJ, 2003; reading.