An unlimited lock range DLL for clock generator

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2004, Pages

  Kim, Kwangoh ^a   Park, Nohman ^a   Kim, Taekyu ^a  

^a Dawintech Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FREQUENCY HOPPING; GATES (TRANSISTOR); INTEGRATED CIRCUITS; JITTER;

DATA RECOVERY; DELAY LOCKED LOOP (DLL); LOOP FILTERS; VOLTAGE CONTROL DELAY LINE (VCDL);

ELECTRIC GENERATORS;

EID: 4344667130     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE Press, Piscataway NJ, 1996.
2. R. B. Watson Jr., and R. B. Iknaian, "Clock buffer chip with multiple target automatic skew compensation," IEEE Jour. Solid-State Circuit, vol. 30, No. 11, pp. 1267-1276, Nov. 1995.
3. W. F. EGAN, Phase-Lock Basics, JohnWiley&Sons, 1998.
4. Chulwoo Kim, Inchul Hwang, and Sung-Mo(Steve) Rang "A Low-Power Small Area ±7.28-ps-jitter 1-GHz DLL-Based Clock Generator," IEEE Jour. Solid-State Circuit, vol. 37, No. 11, pp. 1414-1420, Nov. 2002.
5. D. J. Foley, and M. P. Flynn, "CMOS DLL-Based 2-V 3.2-ps jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator," IEEE Jour. Solid-State Circuit, vol. 36, No. 3, pp. 417-423, Mar. 2001.
6. H. H. Chang, J. W. Lin, C. Y. Yang, and S. I. Liu, "CMOS DLL-Based 2-V 3.2-ps jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator," IEEE Jour. Solid-State Circuit, vol. 36, No. 3, pp. 417-423, Mar. 2001.