Improvements in biasing and compensation of CMOS OPAMPs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Nicolson, Sean ^a   Phang, Khoman ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; MATHEMATICAL MODELS; MOSFET DEVICES; RESISTORS;

COMPENSATION CAPACITORS; CONSTANT-GM BIAS CIRCUITS; DRAIN CURRENTS; GATE-SOURCE VOLTAGES;

CMOS INTEGRATED CIRCUITS;

EID: 4344641971     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. A. McLaren, and K. Martin, "Generation of Accurate On-Chip Time Constants and Stable Transconductances," IEEE Journal of Solid-State Circuits, vol. 36, no. 4, April 2001.
3. A.I.A. Cunha, M.C. Schneider, C. Galup-Montoro, "An MOS transistor model for analog circuit design," IEEE Journal of Solid-State Circuits, vol. 33, no. 10, Oct. 1998.
4. J. M. Steininger, "Understanding wide-band MOS transistors," IEEE Circuits and Devices, vol. 6, pp. 26-36, May 1990.
5. T. Pialis, "Design and Analysis Techniques for Low-Voltage, Low-Jitter Voltage-Controlled Oscillators," M.Eng. Design Project Report, University of Toronto, Department of Electrical Engineering, Toronto, 2002.