5V-only, standard .5um CMOS programmable and adaptive floating-gate circuits and arrays using CMOS charge pumps

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2004, Pages

  Hooper, Mark ^a   Kucic, Matt ^a   Hasler, Paul ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE FLOATING GATE CIRCUITS; CHARGE PUMPS; MODULATE TUNNELING;

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; EXTRAPOLATION; INTEGRATED CIRCUIT LAYOUT; MODULATION; PROGRAMMED CONTROL SYSTEMS; VOLTAGE MEASUREMENT;

PUMPS;

EID: 4344575838     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Kahng and S.M. Sze, A Floating Gate and its Application to Memory Devices, Bell Syst. Tech. J., vol. 46, no. 4, pp. 1288-1295, 1967.
2. J.S. Witters et Al., Analysis and Modeling of On-Chip High-Voltage Generator Circuits for Use in EEPROM Circuits, IEEE JSSC, Vol.24, No.5, 1989, pp.1372-1380.
3. O. Khouri et Al., Improved Charge Pump for Flash Memory Applications in Triple Well CMOS Technology, IEEE ISIE 2002, Vol. 4 pp.8-11.
4. O. J. Shor, Self Regulated Four-Phased Charge Pump with Boosted Wells, IEEE ISCAS, 2003, Vol.1, pp.241-244.
5. K. Sawada et Al., An On-Chip high Voltage Generator Circuit for EEPROMs with a Power Supply Voltage below 2V, 1995 Symposium on VLSI Circuiuts Digest of Technical Papers, 1995, pp.75-76.
6. J.F. Dickson, On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique, IEEE JSSC, Vol. SC-11, No.3, 1976, pp. 374-378.
7. K.H. Cheng et Al., A CMOS Charge Pump for Sub 2V Operation, IEEE ISCAS, 2003, Vol. 5, pp.89-92.
8. M. Hooper, M. Kucic, P. Hasler, Characterization of Charge Pump Rectifiers for Standard Submicron CMOS Processes, IEEE ISCAS 2004.