On designing digit multipliers

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2002, Pages 951-954

  Nibouche, O ^a   Nibouche, M ^b  

^a UNIVERSITY OF ULSTER   (United Kingdom)

^b University of the West   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LEVEL; DIGIT MULTIPLIERS; FEED-BACK LOOP; HARDWARE COST; HIGH RADIX; THROUGHPUT RATE; UNFOLDING TECHNIQUES;

ADDERS;

ARCHITECTURE;

EID: 4344564367     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046406     Document Type: Conference Paper

References (11)

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3. A. S. Ashur, "New Efficient Multiplication Structures and their Applications". Ph.D. thesis, Dept.of Electrical and Electronic Eng., the University of Nottingham, 1995
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5. Y. N. Chang, J. H. Satyanarayana, and K. K. Parhi. "Low-power digit-serial multipliers", IEEE International Symp. On Circuits and Systems (ISCAS), pp. 1023-1026, Hong Kong, June 1997.
6. Y. N. Chang, J.H. Satyanarayana, and K.K. Parhi, "Design and Implementation of Low- Power Digit-Serial Multipliers", Proc. of IEEE Conf. On Computer Design, pp. 186-195, Austin, October 12-15, 1997.
7. R.I. Hartley and K. K. Parhi. Digit-Serial Computation. Kluwer Academic, Boston, MA, 1995.
8. K. K. Parhi, A systematic approach for the design of digit-serial signal processing architectures", IEEE Trans. Circuits and Systems, 38(4), 358-375, Apr. 1991.
9. K. K. Parhi, "VLSI Digital Signal Processing Systems: Design and Implementation", A Wiley-Interscience Publication, 1999.
10. R. Hartley, and P. Corbett, "Digit-Serial Processing Techniques". IEEE Trans. On Circuits and Systems, Vol.37, No.6, pp. 707-719, June 1990.
11. O. Nibouche, A. Bouridane, M. Nibouche, and D. Crookes. "A New Pipelined Digit Serial-Parallel Multiplier", IEEE International Symp. On Circuits and Systems (ISCAS), Geneva 2000.