New class of depth-size optimal parallel prefix circuits

Journal of Supercomputing

Volumn 14, Issue 1, 1999, Pages 39-52

  Lin, Yen Chun ^a   Shih, Chao Cheng ^a  

^a NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; PARALLEL PROCESSING SYSTEMS; THEOREM PROVING; VLSI CIRCUITS;

DEPTH SIZE OPTIMAL; PARALLEL PREFIX CIRCUITS; UNBOUNDED FAN OUT;

COMBINATORIAL CIRCUITS;

EID: 0032593423     PISSN: 09208542     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008147229964     Document Type: Article

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