A new approach to constructing optimal prefix circuits with small depth

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN

Volumn 2002-January, Issue , 2002, Pages 99-104

  Lin, Yen Chun ^a   Hsiao, Jun Wei ^a  

^a NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

Combinational circuits; Computer applications; Computer science; Concurrent computing; Costs; Energy consumption; Parallel architectures; Processor scheduling; Sorting; Very large scale integration

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER APPLICATIONS; COMPUTER SCIENCE; COSTS; ENERGY UTILIZATION; INTEGRATED CIRCUITS; NETWORK ARCHITECTURE; PARALLEL ARCHITECTURES; SORTING;

CIRCUIT PARAMETER; CONCURRENT COMPUTING; DEPTH-SIZE OPTIMAL; OPERATION NODES; PREFIX COMPUTATION; PRIMITIVE OPERATIONS; PROCESSOR SCHEDULING; VLSI IMPLEMENTATION;

VLSI CIRCUITS;

EID: 84947212415     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPAN.2002.1004267     Document Type: Conference Paper

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