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Volumn 6521, Issue , 2007, Pages

Model-based approach for design verification and co-optimization of catastrophic and parametric-related defects due to systematic manufacturing variations

Author keywords

[No Author keywords available]

Indexed keywords

CO-OPTIMIZATION; MANUFACTURABLE DESIGN; MODEL-BASED HOTSPOT DETECTION; PRINTABILITY CHECKER; SILICON-AWARE PARAMETRIC ANALYSIS;

EID: 35148843246     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.712471     Document Type: Conference Paper
Times cited : (10)

References (10)
  • 1
    • 33646043420 scopus 로고    scopus 로고
    • Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap
    • MAY
    • Scott E. Thompson et al., "Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
    • (2006) IEEE TRANSACTIONS ON ELECTRON DEVICES , vol.53 , Issue.5
    • Thompson, S.E.1
  • 2
    • 41149150331 scopus 로고    scopus 로고
    • 1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations
    • Paul Grudowski et al., "1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations", 2006 Symposium on VLSI Technology Digest of Technical Papers
    • (2006) Symposium on VLSI Technology Digest of Technical Papers
    • Grudowski, P.1
  • 3
    • 33744723814 scopus 로고    scopus 로고
    • pMOSFET With 200% Mobility Enhancement Induced by Multiple Stressors
    • JUNE
    • Lori Washington et al., "pMOSFET With 200% Mobility Enhancement Induced by Multiple Stressors", IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 6, JUNE 2006 511
    • (2006) IEEE ELECTRON DEVICE LETTERS , vol.27 , Issue.6 , pp. 511
    • Washington, L.1
  • 4
    • 84942113465 scopus 로고    scopus 로고
    • Nagaraj NS et al., Benchmarks for Interconnect Parasitic Resistance and Capacitance, ISQED 2003
    • Nagaraj NS et al., "Benchmarks for Interconnect Parasitic Resistance and Capacitance", ISQED 2003
  • 7
    • 33745798166 scopus 로고    scopus 로고
    • Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis
    • references contained therein
    • P. Gupta, A. Kahng, Y. Kim, S. Shah, and D. Sylvester, "Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis", Proc. of SPIE, Vol. 6156, 2006, pp. 285-294. (references contained therein)
    • (2006) Proc. of SPIE , vol.6156 , pp. 285-294
    • Gupta, P.1    Kahng, A.2    Kim, Y.3    Shah, S.4    Sylvester, D.5
  • 8
    • 0023983720 scopus 로고
    • Inverse-Narrow-Width Effects and Small-Geometry MOSFET Threshold Voltage Model
    • March
    • K.K-L. Hsueh, J. J. Sanchez, T. A. Demassa, and L. A. Akers, "Inverse-Narrow-Width Effects and Small-Geometry MOSFET Threshold Voltage Model", IEEE Trans. Electron Devices, Vol. 35, No. 3, March 1988, pp. 325-338.
    • (1988) IEEE Trans. Electron Devices , vol.35 , Issue.3 , pp. 325-338
    • Hsueh, K.K.-L.1    Sanchez, J.J.2    Demassa, T.A.3    Akers, L.A.4
  • 9
    • 6344280061 scopus 로고    scopus 로고
    • S.B. Chiah, X. Zhou, and K.Y. Lim, Unified Length-A/Width-Dependent Threshold Voltage Model with Reverse Short-Channel and Inverse Narrow-Width Effects, Nanotech 2003, 2, Cambridge, MA, 2003, pp. 338-341.
    • S.B. Chiah, X. Zhou, and K.Y. Lim, "Unified Length-A/Width-Dependent Threshold Voltage Model with Reverse Short-Channel and Inverse Narrow-Width Effects", Nanotech 2003, Vol. 2, Cambridge, MA, 2003, pp. 338-341.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.