On modeling of parallel repeater-insertion methodologies for SoC interconnects

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 1, 2008, Pages 322-335

  Awwad, Falah R ^a   Nekili, Mohamed ^b   Ramachandran, Venkatanarayama ^b   Sawan, Mohamad ^c  

^a UNITED ARAB EMIRATES UNIVERSITY   (United Arab Emirates)

^b Dept of Electrical and Computer Engineering   (Canada)

^c ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

Delay; Integrated circuit interconnections; Integrated circuit modeling; Interconnects; Mathematical model; Modeling; Parallel Repeaters; Repeaters; System on a chip; VLSI SoC; Wire

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; INDUCTANCE; MATHEMATICAL MODELS; MATLAB; SPICE; TELECOMMUNICATION REPEATERS; TRANSFER FUNCTIONS; VLSI CIRCUITS;

PARALLEL REPEATERS; SYSTEM-ON-CHIP INTERCONNECTS;

INTEGRATED CIRCUITS;

EID: 42949087946     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.910538     Document Type: Article

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