Pessimism reduction in static timing analysis using interdependent setup and hold times

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 159-164

  Salman, Emre ^a   Dasdan, Ali ^b   Taraporevala, Feroze ^b   Kucukcakar, Kayhan ^b   Friedman, Eby G ^a  

^a University of Rochester   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HOLD TIME; INDUSTRIAL CIRCUITS; SET-UP TIME; SIGN-OFF; STATIC TIMING ANALYSIS;

TOOLS;

EID: 42649144705     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.100     Document Type: Conference Paper

References (9)

1. W. Roethig, "Library Characterization and Modeling for 130 nm and 90 nm SOC Design," Proceedings of the IEEE International SOC Conference, pp. 383-386, September 2003.
2. D. Patel, "CHARMS: Characterization and Modeling System for Accurate Delay Prediction of ASIC Designs," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 9.5.1 -9.5.6, May 1990.
3. R. W. Phelps, "Advanced Library Characterization for High-Performance ASIC," Proceedings of the IEEE International ASIC Conference, pp. 15-3.1 -15-3.4, September 1991.
4. V. Stojanovic and V.G. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems," IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, pp. 536-548, April 1999.
5. N. Weste and D. Harris, CMOS VLSI Design, Addison Wesley, 2004.
6. M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures, Princeton University Press, 1992.
7. G. Rao and K. Howick, "Apparatus for Optimized Constraint Characterization with Degraded Options and Associated Methods.," US Patent No. 6,584,598 B2, June 24 2003.
8. H. G. Eggleston, Convexity, Cambridge University Press, 1958.
9. F. P. Preparata and M. I. Shamos, Computational Geometry, Springer-Verlag, 1985.