Stack sizing for optimal current drivability in subthreshold circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 5, 2008, Pages 598-602

  Keane, John ^a   Eom, Hanyong ^a   Kim, Tae Hyoung ^a   Sapatnekar, Sachin ^a   Kim, Chris ^a  

^a University of Minnesota   (United States)

Author keywords

Logical effort; Subthreshold logic; Ultra low power design

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; MOS DEVICES; TRANSISTORS;

CURRENT DRIVABILITY; LOGICAL EFFORT; SUBTHRESHOLD LOGIC; ULTRA LOW POWER DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 42649108070     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.917571     Document Type: Article

References (7)

1. A. Wang and A. P. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
2. T.-H. Kim, J. Liu, J. Keane, and C. H. Kim, "A high-density sub-threshold SRAM with data independent bitline leakage and virtual ground replica scheme," in Proc. Int. Solid-State Circuits Conf., Feb. 2007, pp. 330-331.
3. C. H.-I. Kim, H. Soeleman, and K. Roy, "Ultra-low-power DLMS adaptive filter for hearing aid applications," IEEE Trans. Veiy Large Scale Integr. (VLSI) Syst., vol. 11, no. 6, pp. 1058-1067, Dec. 2003.
4. E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operations," IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224-231, Jun. 1977.
5. The Nanoscale Integration and Modeling Group, Tempe, AZ, "Predictive technology model," 2007 [Online]. Available: http://www.eas.asu.edu/~ptm/
6. W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45 nm design exploration," in Proc. Int. Symp. Quality Electron. Des., 2006, pp. 585-590.
7. D. Harris, R. F. Sproull, and I. E. Sutherland, Logical Effort: Designing Fast CMOS Circuits. San Francisco, CA: Morgan Kaufmann, 1999.