Implementation of high-k and metal gate materials for the 45 nm node and beyond: Gate patterning development

Microelectronics Reliability

Volumn 45, Issue 5-6, 2005, Pages 1007-1011

  Beckx, S ^a   Demand, M ^a   Locorotondo, S ^a   Henson, K ^a   Claes, M ^a   Paraschiv, V ^a   Shamiryan, D ^a   Jaenen, P ^a   Boullart, W ^a   Degendt, S ^a   Biesemans, S ^a   Vanhaelemeersch, S ^a   Vertommen, J ^a   Coenegrachts, B ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ANTIREFLECTION COATINGS; FIELD EFFECT TRANSISTORS; ION IMPLANTATION; OPTIMIZATION; PLASMA ETCHING; POLYSILICON; TRANSMISSION ELECTRON MICROSCOPY;

GATE PATTERNING DEVELOPMENT; METAL GATES; MULTI-GATE FIELD EFECT TRANSISTORS (MUGFET); SILICON RECESS;

DIELECTRIC MATERIALS;

EID: 20044364928     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.11.005     Document Type: Conference Paper

References (4)

1. 2 layers measured by wet etching J Electrochem Soc 151 11 2004 F269 F275
2. S.A. Vitale, and B.A. Smith Reduction of silicon recess caused by plasma oxidation during high-density plasma polysilicon gate etching J Vac Sci Technol B 21 5 2003 2205
3. Henson K, Lander BR, Demand M, Dachs C, Kaczer B, Deweerd W, et al. NMOS transistors with metal gate on thin SiON driving 1550 μA/μm at 1.3 V and off-state of 70 nA/μm. IEDM, San Francisco, CA, p. 851-854, Dec 13-15, 2004
4. Collaert N, Henson K, Demand M, Goodwin M, Brus S, Rooyackers R, et al. NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics. VLSI-TSA-TECH, submitted for publication