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Volumn 50, Issue 1, 2008, Pages 19-32

A highly parallel joint VLSI architecture for transforms in H.264/AVC

Author keywords

Adaptive block size transforms; H.264 AVC; Very Large Scale Integration (VLSI) design

Indexed keywords

ADAPTIVE BLOCK SIZE TRANSFORMS; CODING TOOLS; LINEAR SHIFT MAPPING; PARALLEL JOINT CIRCUITS;

EID: 42149135421     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-007-0111-4     Document Type: Article
Times cited : (33)

References (8)
  • 6
    • 2042436420 scopus 로고    scopus 로고
    • New Cost-Effective VLSI Implementation of a 2-D Discrete Cosine Transform and Its Inverse
    • D. Gong, Y. He, Z. Cao, "New Cost-effective VLSI Implementation of a 2-D Discrete Cosine Transform and Its Inverse", IEEE Trans. Circuits Syst. Video Technol., vol. 14, 2004, pp. 405-415 (April).
    • (2004) IEEE Trans. Circuits Syst. Video Technol. , vol.14 , pp. 405-415
    • Gong, D.1    He, Y.2    Cao, Z.3
  • 7
    • 84864175914 scopus 로고    scopus 로고
    • A highly parallel cost-effective VLSI implementation for 8∈×∈8 transform in H.264/AVC
    • Beijing (April)
    • Y. Li, Y. He, "A Highly parallel Cost-effective VLSI Implementation for 8∈×∈8 Transform in H.264/AVC", Proceedings of PCS2006, Beijing, 2006 (April).
    • (2006) Proceedings of PCS2006
    • Li, Y.1    He, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.