Modeling and characterization of bias stress-induced instability of SiC MOSFETs

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2006, Pages 160-162

  Lelis, A J ^a   Potbhare, S ^b   Habersat, D ^a   Pennington, G ^b   Goldsman, N ^b  

^a U S ARMY RESEARCH LABORATORY   (United States)

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; COMPUTER SIMULATION; SILICON CARBIDE; STRESS ANALYSIS; THRESHOLD VOLTAGE;

BIAS STRESSING; CIRCUIT PERFORMANCE;

MOSFET DEVICES;

EID: 41649091818     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2006.305235     Document Type: Conference Paper

References (7)

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2. A.J. Lelis, D. Habersat, G. Lopez, J.M. McGarrity, F.B. McLean, and N. Goldsman, "Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs," Materials Sci. Forum (Proc. of the 2005 ICSCRM), to he published.
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7. S. Potbhare, N. Goldsman, G. Pennington, A. Lelis, and J. M. McGarrity, "Numerical and experimental characterization of 4H-silicon carbide lateral metal-oxide-semiconductor field-effect transistor", J. of Applied Physics, 100, 044515 (2006)