Some results on taylor-series function approximation on FPGA

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2003, Pages 2198-2202

  Lee, Barry ^a   Burgess, Neil ^a  

^a CARDIFF UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; APPROXIMATION THEORY; COSINE TRANSFORMS; FUNCTIONS; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; OPTIMIZATION; PROBLEM SOLVING; PRODUCT DESIGN; ROM; TABLE LOOKUP;

LOGIC REDUCTION; OPERANDS; TAYLOR SERIES EXPANSION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 4143129045     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. th Symp. On Computer Arith., 2001. pages 128-135.
2. J. Detrey and F. Dinechin, "Multipartite Tables in Jbits for the evaluat ion of Functions on FPGAs", Proc. International Parallel and distributed Processing Symp. 2002
3. D. Defour, F. Dinechin and I. M. Muller, "A new scheme for table-based evaluation of functions", INRIA-ENS research report No 2002-45. Nov, 2002.
4. J. A. Pineiro, J.D. Bruguera and J. M. Muller, "FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation", In Euromicro Symp. on Digital sys., Design. 2001. pages 262-269.
5. th Asilomar Conference on Sig, Sys. and Comps. 2002.
6. M. R. Spiegel and J. Liu, "Mathematical Handbook of Formulas and Tables", McGraw-Hill, USA, 1999.
7. Xilinx, "The Virtex-II Logic Data Book", Xilinx, San Jose, 2000.
8. Altera, "Stratix FPGA Family Data Sheet", Altera, San Jose, 2002.