DSP system design using the BEE hardware emulation environment

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2003, Pages 895-899

  Richards, Brian ^a   Chang, Chen ^a   Brodersen, Robert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BERKELEY EMULATION ENGINE (BEE) SYSTEMS; DIGITAL SIGNAL PROCESSING (DSP) SYSTEM DESIGNS; ULTRA WIDE-BAND SYSTEMS; WIRELESS BASEBAND DESIGNS; XILINX SYSTEM GENERATOR TOOLS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLIENT SERVER COMPUTER SYSTEMS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS; GRAPHICAL USER INTERFACES; IMAGE COMPRESSION; MAPPING; PROGRAM DEBUGGING; RAPID PROTOTYPING; TRANSCEIVERS;

SYSTEMS ANALYSIS;

EID: 4143101167     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. W.R. Davis, N. Zhang, et al., "A Design Environment for High-Throughput, Low-Power Dedicated Signal Processing Systems," IEEE J. Solid-State Circuits, Vol. 37, March 2002.
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3. www.xilinx.com.
4. C. Chang, K. Kuusilinna, B. Richards, R. W. Brodersen, "Implementation of BEE: a Real-time Large-scale Hardware Emulation Engine," Proc. FPGA 2003, Feb. 2003
5. L. Bahl, J. Cocke, F. Jelinek, and R. Raviv, "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate," IEEE Trans. Information Theory, vol. 20, no. 2, pp. 284-287, Mar 1974.
6. E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "VLSI architectures for iterative decoders in magnetic recording channels," IEEE Trans. Magnetics, vol. 37, no. 2, pp. 748-755, Mar. 2001.
7. www.st.com