Integration of self-formed barrier technology for 32nm-node Cu dual-damascene interconnects with hybrid low-k (PAr/SiOC) structure

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 114-115

  Ohoka, Y ^a   Inoue, K ^a   Hayashi, T ^a   Komai, N ^a   Arakawa, S ^a   Kanamura, R ^a   Kadomura, S ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DIELECTRIC FILMS; ELECTROMIGRATION; INTEGRATED CIRCUIT LAYOUT; PERMITTIVITY; TRANSMISSION ELECTRON MICROSCOPY; X RAY PHOTOELECTRON SPECTROSCOPY;

DUAL-DAMASCENE INTERCONNECTS; SELF FORMED BARRIER TECHNOLOGY;

INTERCONNECTION NETWORKS;

EID: 41149178704     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. T. Usui et al., Proc. of IITC(2005) pp.188
2. J. Koike et al., Appl. Phys. Lett. 87, p41911(2005)
3. R. Kanamura et al., Proc. of VLSI Tech. (2003) pp107