Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/ SiOC Hybrid Structure for 65nm-node High Performance eDRAM

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 107-108

  Kanamura, R ^a   Fukasawa, Y Ohoka M ^a   Tabuchi, K ^a   Nagahata, K ^a   Shibuki, S ^a   Muramatsu, M ^a   Miyajima, H ^b   Usui, T ^b   Kajita, A ^b   Shibata, H ^b   Kadomura, S ^a  

^a SONY CORPORATION   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC RESISTANCE; FAILURE ANALYSIS; PERMITTIVITY; SILICON COMPOUNDS; TRANSMISSION ELECTRON MICROSCOPY;

THERMAL GROWTH;

ELECTRIC CONNECTORS; INTEGRATED CIRCUIT INTERCONNECTS;

65-NM-NODE; CU/LOW-K; DUAL DAMASCENE INTERCONNECT; EMBEDDED DRAM; HARDMASKS; HYBRID DUAL DAMASCENE; HYBRID STRUCTURE; LOW-K DUAL DAMASCENE INTERCONNECTS; MASK PROCESS; PERFORMANCE;

EID: 0141538321     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S. M. Jang et al., Symp. on VLSI Tech. (2002) pp. 19.
2. S. Purashothaman et al., IEDM Tech. Dig. (2001) pp. 23.
3. K. Higashi et al., Proc. of IITC (2002) pp. 15.
4. M. Ikeda et al., Materials Trans., 43 (2002) pp.1577.