An ultra-wide range digitally adaptive control phase locked loop with new 3-phase switched capacitor loop filter

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 33-34

  Dosho, Shiro ^a   Yanagisawa, Naoshi ^a   Sogawa, Kazuaki ^a   Yamada, Yuji ^a   Morie, Takashi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 39749156515     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. John G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, vol. 31, NO. 11, pp. 1723-1732, November 1996.
2. John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, and Manjusha Shankaradas, "Self-Biased High-Bandwidth Low-Jitter l-to-4096 Multiplier Clock Generator PLL," IEEE Journal of Solid-State Circuits, vol. 38, pp. 1795-1803, November 2003.
3. Adrian Maxim, Baker Scott, Edmund M. Schneider, Melvin L. Hagge, Steven Chacko, and Dan Stiurca, "A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-um CMOS PLL Based on a Sample-Reset Loop Filter," IEEE Journal of Solid-State Circuits, vol. 36, NO. 11, pp. 1673-1683, November 2001.
4. T.Lee and B. Razavi, "A stabilization technique for phase-locked frequency synthesizer," in Proc. 2001 Symp. VLSI Circuits, Kyoto, Japan, June 2001, pp.39-42