A 5 kV HBM transformer-based ESD protected 5-6 GHz LNA

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 100-101

  Borremans, J ^a,b   Thijs, S ^b   Wambacq, P ^a,b   Linten, D ^b   Rolain, Y ^a   Kuijk, M ^a  

^a VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^b IMEC   (Belgium)

Author keywords

CMOS; ESD protection; LNA; Low area; Transformer

Indexed keywords

ELECTRIC BREAKDOWN; MOS CAPACITORS;

ESD PROTECTION; MOS TRANSISTOR;

CMOS INTEGRATED CIRCUITS;

EID: 39749155918     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342677     Document Type: Conference Paper

References (8)

1. S. Galal, B. Razavi, '40-Gb/s Amplifier and ESD protection circuit in 0.18-μm CMOS technology', JSSC, Vol. 39, No. 12, December 2004.
2. D. Linten et al, 'An Integrated 5 GHz low-noise amplifier with 5.5 kV HBM ESD protection in 90 nm RF CMOS', VLSI Circuits Symposium, June 2005, pp. 86-89.
3. L. F. Tiemeijer et al, "The Impact of an Aluminum Top Layer on Inductors Integrated in an Advanced CMOS Copper Backend", IEEE Electron Device Letters, Vol. 25, No. 11, November 2004, pp. 722-724.
4. ASITIC, http://rfic.eecs.berkeley.edu/~niknejad/asitic.html
5. HFSS, www.ansoft.com/products/hf/hfss/
6. [61 D. K. Shaeffer, T. H. Lee, 'A 1.5-V, 1.5-GHz CMOS low noise amplifier', JSSC, Vol. 32, No 5, May 1997 pp.745-759.
7. J. Long, 'Monolithic Transformers for Silicon RF IC Design', JSSC, Vol. 35, No. 9, Sept. 2000, pp.1368-1382.
8. S. Hyvonen, E. Rosenbaum, 'Diode-Based Tuned ESD Protection for 5.2 5 GHz CMOS LNAs', EOS/ESD Symposium, September 2005, pp.9-17.