A CMOS ΔΣ fractional-N frequency synthesizer with quantization noise pushing technique

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 262-263

  Yang, Yu Che ^a   Lu, Shey Shi ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

; Frequency synthesizer and phase locked loops; Quantization noise

Indexed keywords

ELECTRIC POWER UTILIZATION; FREQUENCY SYNTHESIZERS; MODULATORS; PHASE NOISE;

BAND PHASE NOISE; NOISE PUSHING TECHNIQUES; QUANTIZATION NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 39749151140     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342743     Document Type: Conference Paper

References (5)

1. S. K. Meninger and M. H. Perrott, "A 1-MHz Bandwidth 3.6-GHz 0.18-um CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise," J. Solid-State Circuits, vol. 41, pp. 966-980, April 2006.
2. H. Huh, et al., "A CMOS Dual-Band Fractional-N Synthesizer with Reference Doubler and Compensated Charge Pump," ISSCC Dig. Tech. Papers, pp. 100-101, Feb. 2004.
3. D. Banerjee, PLL performance, simulation, and design, National Semiconductor, Available: http://webench.national.com/appinfo/wireless/files/ deansbook4.pdf
4. Y. Sumi, "A New Frequency Synthesizer Using Multi-Programmable Divider," IEEE Transaction on Consumer Electronics, vol. 44, pp.827-832, Aug. 1998.
5. M. Marutani, et al., "An 1.8mW 90 to 770MHz Synthesizer with Agile Auto-Tuning for Digital TV-Tuners," ISSCC Dig. Tech. Papers, paper no. 11.1, Feb. 2006