A new PLL frequency synthesizer using multi-programmable divider

IEEE Transactions on Consumer Electronics

Volumn 44, Issue 3, 1998, Pages 827-832

  Sumi, Yasuaki ^a   Syoubu, Kouichi ^b   Obote, Shigeki ^b   Fukui, Yutaka ^b   Itoh, Yoshio ^b  

^a SANYO ELECTRIC CO LTD   (Japan)

^b TOTTORI UNIVERSITY   (Japan)

Author keywords

Higher speed lock up time; Multiprogrammable divider; Pll frequency synthesizer

Indexed keywords

FREQUENCY DIVIDING CIRCUITS; PHASE LOCKED LOOPS;

SPEED LOCK-UP TIME;

FREQUENCY SYNTHESIZERS;

EID: 0032135939     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.713201     Document Type: Article

References (8)

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