A 14-b 150 MS/s CMOS DAC with digital background calibration

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 51-52

  Chen, Hsin Hung ^a   Lee, Jaesik ^b   Weiner, Joe ^b   Chen, Young Kai ^b   Chen, Jiunn Tsair ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

Background calibration; Digital calibration; Digital to analog converter

Indexed keywords

CALIBRATION; DIGITAL TO ANALOG CONVERSION;

BACKGROUND CALIBRATION; DIGITAL BACKGROUND CALIBRATION LOOP; DIGITAL CALIBRATION; SPURIOUS FREE DYNAMIC RANGE (SFDR);

CMOS INTEGRATED CIRCUITS;

EID: 39749108049     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Bastos, J.; Marques, A.M.; Steyaert, M.S.J.; Sansen, W., "A 12-b Intrinsic Accuracy High-Speed CMOS DAC", IEEE J. Solid-State Circuits, pp. 1959-1969, Dec. 1998.
2. D. W. J. Groenveld et al., "A Self-Technique for Monolithic Hign-Resolution D/A Converters," IEEE J. Solid-State Circuits, vol. 24, pp. 1517-1522, Dec. 1989.
3. A. Bugeja and B. Song, "A Self-Trimming 14-B 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, pp. 1841-1852, Dec. 2000.
4. K. Falakshahi et al., "A 14-b 10MS/s DAC Using Multibit ZA Modulation," IEEE JSSC, vol. 34, pp. 607-615, May. 1999.