Efficiency of low-power design techniques in multi-gate FET CMOS circuits

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 111-114

  Pacha, C ^a   Von Arnims, K ^a   Bauer, F ^a   Schulz, T ^a   Xiong, W ^b   San, K T ^b   Marshall, A ^b   Baumann, T ^a   Cleavelin, C R ^b   Schruefer, K ^a   Berthold, J ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; LOGIC GATES; SCALABILITY;

CLOCK FREQUENCIES; MULTI-GATE FET (MUGFET); POWER DESIGN; VOLTAGE SCALABILITY;

CMOS INTEGRATED CIRCUITS;

EID: 39549120886     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430891     Document Type: Conference Paper

References (6)

1. C. Pacha et al., "Circuit Design Issues in Multi-Gate FET CMOS Technologies", ISSCC Dig. Techn. Papers, pp. 420, 2006.
2. G. Knoblinger et al., "Multi-Gate MOSFET Design," Proc. of ESSCIRC, 2006, pp. 66-69.
3. B. Doyle et al., "Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout", VLSI Techn. Symp., 2006, pp. 133-134.
4. K. v. Arnim et al., "A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay", VLSI Tech. Symp. 2007 to be published.
5. T. Lueftner et al., "A 90nm CMOS Low Power GSM/EDGE Multimeda Enhanced Baseband Processor", ISSCC Dig. Techn. Papers, pp. 253, 2006.
6. W. Xiong et al., "Intrinsic Advantages of SOI Multiple-Gate MOSFET for Low Power Applications", 211th Electrochem. Soc. Meeting, 2007.