A code-generator generator for multi-output instructions

CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2007, Pages 131-136

  Scharwaechter, Hanno ^a   Leupers, Rainer ^a   Ascheid, Gerd ^a   Meyr, Heinrich ^a   Youn, Jonghee M ^b   Paek, Yunheung ^b  

^a RWTH AACHEN UNIVERSITY   (Germany)

^b Seoul National University   (South Korea)

Author keywords

ASIP; Code selection; Compiler architecture co design; ISS

Indexed keywords

COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSORS; HEURISTIC ALGORITHMS; PROBLEM SOLVING; PROGRAM COMPILERS;

COMPILER ARCHITECTURE CO-DESIGN; MULTI OUTPUT INSTRUCTIONS;

AUTOMATIC PROGRAMMING;

EID: 38949093175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289816.1289851     Document Type: Conference Paper

References (24)

1. A. V. Aho, M. Ganapathi, and S. W. K. Tjiang. Code Generation Using Tree Pattern Matching and Dynamic Programing. ACM Transactions on Programming Languages and Systems., 11(4):491-516, Oct. 1989.
2. O. Araujo, S. Malik, and M. Lee. Using Register Transfer Paths in Code Generation for Heterogeneous Memory Register Architectures. In Proc. of the Design Automation Conference (DAC), pages 591-596, June 1996.
3. C. Fraser and D. Hanson. A Retargetable C Compiler : Design and Implementation. Benjamin/Cummings Publishing Co., 1994.
4. N. Clark, A. Hormiri, S. Mahlke, and S. Yehia. Scalable Subgraph Mapping for Acyclic Computation Accelerators. In Proc. of the Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Oct. 2006.
5. C. Devine, http://xyssl.org, 2007.
6. E. Eckstein, O. Koening, and B. Scholz. Code Instruction Selection Based on SSA Graphs. In Proc. of the Workshop on Software and Compilers for Embedded Systems (SCOPES), pages 49-65, Oct. 2003.
7. M. A. Ertl. Optimal Code Selection in DAGs. In "Principles of Programming Languages(POPL '99)", 1999.
8. C. W. Fraser, D. R. Hanson, and T. A. Proebsting. Engineering Efficient Code Generators Using Tree Matching and Dynamic Programming. Technical Report TR-386-92, 1992.
9. C. W. Fraser, R. R. Henry, and T. A. Proebsting. BURG-fast optimal instruction selection and tree parsing. Technical Report CS-TR-1991-1066, 1991.
10. M. R. Garey and D. S. Johnson. A Guide to the Theory of NP-Completeness. W. H. Freeman & CO, New York, 1990. ISBN:0716710455.
11. A. Halambi, P. Grun, V Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. In Proc. of the Conference on Design, Automation & Test in Europe (DATE), Mar. 1999.
12. A. Hoffmann, H. Meyr, and R. Leupers. Architecture Exploration for Embedded Processors With Lisa. Kluwer Academic Publishers, Jan. 2003. ISBN 1-4020-7338-0.
13. K. Karuri, M. A. A. Faruque, S. Kraemer, R. Leupers, G. Ascheid., and H. Meyr. Fine-grained Application Source Code Profiling for ASIP Design. In Proc. of the Design Automation Conference (DAC), pages 329-334, 2005.
14. K. Keutzer and H. M. et. al. Building ASIPs: The Mescal Methodology. Springer, June 2005. ISBN: 0-387-26057-9.
15. R. Leupers and P. Marwedel. Instruction Selection for Embedded DSPs with Complex Instructions. In Proc. of the European Conference on Design Automation (EDAC), Sept 1996.
16. S. Liao, S. Devadas, K. Keutzer, and S. Tjiang. Instruction Selection Using Bínate Covering for Code Size Optimization. In Proc. of the Int. Conf on Computer Aided Design (ICCAD), pages 393-399, 1995.
17. C. Liem, T. May, and P. Paulin. Instruction-set Matching and Selection for DSP and ASIP Code Generation. In Proc. of the European Design and Test Conference (ED & TC), pages 31-37, 1994.
18. M. Willems and V. "Živojnović. DSP-Compiler: Product Quality for Control-Dominated Applications? In Proc. of the Int. Conf. on Signal Processing Applications and Technology (ICSPAT), Oct. 1996.
19. MIPS technologies Inc. MIPS 4Kc Processor Core Datasheet, Jun. 2000.
20. S. Kobayashi, Y. Takeuchi, A. Kitajima, M. Imai. Compiler Generation in PEAS-III: an ASIP Development System. In Workshop on Software and Compilers for Embedded Processors (SCOPES), 2001.
21. S. Sakai, M.Togasaki, and K. Yamazaki. A Note on Greedy Algorithms for the Maximum Weighted Independent Set Problem. Discrete Applied Mathematics, 126:313-322, 2003.
22. H. Scharwaechter, D. Kammler, A. Wieferink, M. Hohenauer, J. Zeng, K. Karuri, R. Leupers, G. Ascheid, and H. Meyr. ASIP Architecture Exploration for Efficient IPSec Encryption: A Case Study. ACM Transactions on Embedded Computing Systems (TECS), 6(2), Mai 2007.
23. S. W. K. Tjiang. An Olive Twig. Technical report, Synopsys Inc., 1993.
24. A. Todd. Least-Cost Instruction Selection in DAGs is NP-Complete. In "http://research.microsoft.com/~toddpro/papers/proof.htm", Feb. 2007.