Monolithic pixel detector in a 0.15μm SOI technology

IEEE Nuclear Science Symposium Conference Record

Volumn 3, Issue , 2006, Pages 1440-1444

  Arai, Y ^a,b   Hazumi, M ^b   Ikegami, Y ^b   Kohriki, T ^b   Tajima, O ^b   Terada, S ^b   Tsuboyama, T ^b   Unno, Y ^b   Ushiroda, H ^b   Ikeda, H ^c   Hara, K ^d   Ishino, H ^e   Kawasaki, T ^f   Martin, E ^g   Varner, G ^g   Tajima, H ^h   Ohno, M ⁱ   Fukuda, K ⁱ   Komatsubara, H ⁱ   Ida, J ⁱ   Hayashi, H ⁱ   more..

^a IEEE

^b INSTITUTE OF PARTICLE AND NUCLEAR STUDIES   (Japan)

^c JAPAN AEROSPACE EXPLORATION AGENCY   (Japan)

^d UNIVERSITY OF TSUKUBA   (Japan)

^e TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^f NIIGATA UNIVERSITY   (Japan)

^g UNIVERSITY OF HAWAII   (United States)

^h SLAC NATIONAL ACCELERATOR LABORATORY   (United States)

ⁱ Oki Electric Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRODES; IMAGE ANALYSIS; PIXELS; SENSORS; SILICON ON INSULATOR TECHNOLOGY;

PIXEL DETECTORS; SUBSTRATE IMPLANTS;

SEMICONDUCTOR DETECTORS;

EID: 38649111700     PISSN: 10957863     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NSSMIC.2006.354171     Document Type: Conference Paper

References (8)

1. SOITEC, http://www.soitec.com/
2. X. Llopart et al., "Medipix2: a 64-k Pixel Readout Chip With 55-um Square Elements Working in Single Photon Counting Mode", IEEE Trans. Nucl. Sci., Vol. 49, (2002) 2279-2283.
3. J. R. Schwank, V. Ferlet-Cavrois, M. R. Shaneyfelt, P. Paillet, and P. E. Dodd, "Radiation Effects in SOI Technologies", IEEE Trans. on Nucl. Sci., Vol. 50, (2003) 522-538.
4. A. Makihara et al, "Hardness-by-Design Approach for 0.15 mm Fully Depleted CMOS/SOI Digital Logic Devices With Enhanced SEU/SET Immunity", IEEE Trans. on Nucl. Sci. Vol. 52 (2005) 2524-2530.
5. B. W. Offord and J. S. Ruthberg, "Radiation-Hardened Silicon-on-Insulator 0.8-um Technology Design Rules", Technical Document 3065, 1999, http://www.spawar.navy.mil/sti/publications/pubs/td/3065/td3065.pdf
6. SOI Pixel detector R&D, http://rd.kek.jp/project/soi/
7. Y. Arai et al., "First Results of 0.15um CMOS SOI Pixel Detector", SLAC Electronic Conference Proceedings Archive. http://www.slac.stanford.edu/econf/C0604032/ papers/0016.PDF
8. K. Morikawa and M. Mitarashi, "Low-Power LSI technology of 0.15 um FD-SOI", OKI Technical Review Issue 196, Vol. 70, No. 4, pp. 60-63, Oct. 2003. http://www.oki.com/en/otr/196/downloads/otr-196R15.pdf