Challenges of thermomechanical design and modeling of ultra fine-pitch wafer level packages

Proceedings of the 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2004

Volumn , Issue , 2004, Pages 601-907

  Tay, Andrew A O ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COEFFICIENT OF THERMAL EXPANSION; SILICON CHIPS; UNDERFILLING; WAFER LEVEL PACKAGING;

INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; SILICON WAFERS; STRAIN; THERMAL CYCLING; THERMAL EXPANSION; THERMAL STRESS; THERMOMECHANICAL TREATMENT;

CHIP SCALE PACKAGES;

EID: 3843095999     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. International Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, CA, 2001; http://public.itrs.net/.
2. Vaidyanathan Kripesh and Mahadevan K Iyer, "A Method of Forming Wafer Level Interconnects," U.S. patent filed in March 2003.
3. A. C. Chng, A. A. O. Tay, K. M. Lim, E. H. Wong, K. Vaidyanathan, Fatigue Life Estimation of a Bed-Of-Nails Ultra-Fine-Pitch Wafer Level Package Using the Macro-Micro Modelling Approach, Proceedings EPTC 2003, pp.
4. B. Zhao, A.A.O. Tay, R.R. Tummala, C.P. Wong, Z.Q. Zhang and R. Doraiswami, Simulation of the fatigue life of solder ball joint of an ultra-fine pitch wafer level package, Proceedings of EPTC, 2003, pp 683-687.
5. H. D. Solomon, Fatigue of 60/40 solder, IEEE Transactions on Components, Hybrids and Manufacturing Technology, 9(4), 423-432, 1986.
6. J. S. Corbin, Finite element analysis for Solder Ball Connect (SBC) structural design optimization, IBM Journal of Research and Development, 37(5), pp. 585-596, 1993.
7. H. C. Cheng, K. N. Chiang, M. H. Lee, An effective approach for three-dimensional finite element analysis of ball grid array typed packages, Journal of Electronic Packaging, 120, pp. 129-134, 1998.
8. T. Lee, J. Lee, I. Jung, Finite element analysis for solder ball failures in chip scale package, Microelectronics Reliability, 38, pp. 1941-1947, 1998.
9. Z. N. Cheng, G. Z. Wang, L. Chen, J. Wilde, K. Becker, Viscoplastic Anand model for solder alloys and its application, Solder & Solder Mount Technology, 12(2), pp. 31-36, 2000.
10. J. Zhu, Three-dimensional effects of solder joints in micro-scale BGA assembly, Journal of Electronic Packaging, 121, pp. 297-302, 1999.
11. W. Kim, et al., "Electrical Design of Wafer Level Package on Board For Gigabit Data Transmission," 5th Electronics Packaging Technology Conference (EPTC2003), pp 150-159, Dec. 2003.