Logic circuit synthesis preserving correctness using ET rules

WSEAS Transactions on Circuits and Systems

Volumn 6, Issue 5, 2007, Pages 465-472

  Yoshikawa, Hiroshi ^a   Akama, Kiyoshi ^a   Mabuchi, Hiroshi ^b  

^a HOKKAIDO UNIVERSITY   (Japan)

^b IWATE PREFECTURAL UNIVERSITY   (Japan)

Author keywords

Equivalent transformation; ET rules; Logic circuit synthesis; Rewriting rules

Indexed keywords

EQUIVALENT CIRCUITS; FINITE AUTOMATA; FORMAL LOGIC; MATHEMATICAL TRANSFORMATIONS;

EQUIVALENT TRANSFORMATION; LOGIC CIRCUIT SYNTHESIS; REWRITING RULES;

LOGIC CIRCUITS;

EID: 38349127093     PISSN: 11092734     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (13)

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