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Volumn 4501 LNCS, Issue , 2007, Pages 272-286

Applying logic synthesis for speeding up SAT

Author keywords

[No Author keywords available]

Indexed keywords

CONFORMAL MAPPING; HEURISTIC METHODS; PROBLEM SOLVING; PROGRAM PROCESSORS;

EID: 38049132677     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-72788-0_26     Document Type: Conference Paper
Times cited : (63)

References (16)
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    • A. Biere. AIGER (AIGER is a format, library and set of utilities for And-Inverter Graphs (AIGs)). http://fmv.jku.at/aiger/.
  • 2
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    • DAG-Aware Circuit Compression For Formal Verification
    • P. Bjesse and A. Boralv. DAG-Aware Circuit Compression For Formal Verification. In Proc. ICCAD'04, 2004.
    • (2004) Proc. ICCAD'04
    • Bjesse, P.1    Boralv, A.2
  • 3
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    • DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs
    • D. Chen and J. Cong. DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs. In ICCAD, pages 752-759, 2004.
    • (2004) ICCAD , pp. 752-759
    • Chen, D.1    Cong, J.2
  • 4
    • 38049130459 scopus 로고    scopus 로고
    • R. Drechsler. Using Synthesis Techniques in SAT Solvers. Technical Report, Intitute of Computer Schience, Unversity of Bremen, 28359 Bremen, Germany, 2004.
    • R. Drechsler. Using Synthesis Techniques in SAT Solvers. Technical Report, Intitute of Computer Schience, Unversity of Bremen, 28359 Bremen, Germany, 2004.
  • 5
    • 38049111011 scopus 로고    scopus 로고
    • N. Een. http://www.cs.chalmers.se/~een/SAT-2007.
    • (2007)
    • Een, N.1
  • 6
    • 26444549375 scopus 로고    scopus 로고
    • Effective Preprocessing in SAT through Variable and Clause Elimination
    • th International Conference SAT'2005, of
    • th International Conference (SAT'2005), volume 3569 of LNCS, 2005.
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    • Een, N.1    Biere, A.2
  • 7
    • 38049161017 scopus 로고    scopus 로고
    • N. Een and N. Sörensson. Translating Pseudo-Boolean Constraints into SAT. In Journal on Satisfiability, Boolean Modelling and Computation (JSAT), 2 of IOS Press, 2006.
    • N. Een and N. Sörensson. Translating Pseudo-Boolean Constraints into SAT. In Journal on Satisfiability, Boolean Modelling and Computation (JSAT), volume 2 of IOS Press, 2006.
  • 8
    • 38049139457 scopus 로고    scopus 로고
    • B. L. S. Group. ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/
    • B. L. S. Group. ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/
  • 9
    • 26444437248 scopus 로고    scopus 로고
    • Clause Form Conversions for Boolean Circuits
    • Theory and Appl. of Sat. Testing, 7th Int. Conf, SAT'04, of, Springer
    • P. Jackson and D. Sheridan. Clause Form Conversions for Boolean Circuits. In Theory and Appl. of Sat. Testing, 7th Int. Conf. (SAT'04), volume 3542 of LNCS, Springer, 2004.
    • (2004) LNCS , vol.3542
    • Jackson, P.1    Sheridan, D.2
  • 10
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    • Fast Generation of Irredundant Sum-Of-Products Forms from Binary Decision Diagrams
    • S. Minato. Fast Generation of Irredundant Sum-Of-Products Forms from Binary Decision Diagrams. In Proc. SASIMI'92.
    • Proc. SASIMI'92
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  • 11
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    • DAG-aware AIG rewriting: A fresh look at combinational logic synthesis
    • A. Mishchenko, S. Chatterjee, and R. Brayton. DAG-aware AIG rewriting: A fresh look at combinational logic synthesis. In Proc. DAC'06, pages 532-536, 2006.
    • (2006) Proc. DAC'06 , pp. 532-536
    • Mishchenko, A.1    Chatterjee, S.2    Brayton, R.3
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    • Benchmarking SAT Solvers for Bounded Model Checking
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