-
1
-
-
38049098845
-
-
A. Biere. AIGER (AIGER is a format, library and set of utilities for And-Inverter Graphs (AIGs)). http://fmv.jku.at/aiger/.
-
A. Biere. AIGER (AIGER is a format, library and set of utilities for And-Inverter Graphs (AIGs)). http://fmv.jku.at/aiger/.
-
-
-
-
2
-
-
16244421073
-
DAG-Aware Circuit Compression For Formal Verification
-
P. Bjesse and A. Boralv. DAG-Aware Circuit Compression For Formal Verification. In Proc. ICCAD'04, 2004.
-
(2004)
Proc. ICCAD'04
-
-
Bjesse, P.1
Boralv, A.2
-
3
-
-
16244418071
-
DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs
-
D. Chen and J. Cong. DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs. In ICCAD, pages 752-759, 2004.
-
(2004)
ICCAD
, pp. 752-759
-
-
Chen, D.1
Cong, J.2
-
4
-
-
38049130459
-
-
R. Drechsler. Using Synthesis Techniques in SAT Solvers. Technical Report, Intitute of Computer Schience, Unversity of Bremen, 28359 Bremen, Germany, 2004.
-
R. Drechsler. Using Synthesis Techniques in SAT Solvers. Technical Report, Intitute of Computer Schience, Unversity of Bremen, 28359 Bremen, Germany, 2004.
-
-
-
-
5
-
-
38049111011
-
-
N. Een. http://www.cs.chalmers.se/~een/SAT-2007.
-
(2007)
-
-
Een, N.1
-
6
-
-
26444549375
-
Effective Preprocessing in SAT through Variable and Clause Elimination
-
th International Conference SAT'2005, of
-
th International Conference (SAT'2005), volume 3569 of LNCS, 2005.
-
(2005)
LNCS
, vol.3569
-
-
Een, N.1
Biere, A.2
-
7
-
-
38049161017
-
-
N. Een and N. Sörensson. Translating Pseudo-Boolean Constraints into SAT. In Journal on Satisfiability, Boolean Modelling and Computation (JSAT), 2 of IOS Press, 2006.
-
N. Een and N. Sörensson. Translating Pseudo-Boolean Constraints into SAT. In Journal on Satisfiability, Boolean Modelling and Computation (JSAT), volume 2 of IOS Press, 2006.
-
-
-
-
8
-
-
38049139457
-
-
B. L. S. Group. ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/
-
B. L. S. Group. ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/
-
-
-
-
9
-
-
26444437248
-
Clause Form Conversions for Boolean Circuits
-
Theory and Appl. of Sat. Testing, 7th Int. Conf, SAT'04, of, Springer
-
P. Jackson and D. Sheridan. Clause Form Conversions for Boolean Circuits. In Theory and Appl. of Sat. Testing, 7th Int. Conf. (SAT'04), volume 3542 of LNCS, Springer, 2004.
-
(2004)
LNCS
, vol.3542
-
-
Jackson, P.1
Sheridan, D.2
-
10
-
-
0002896618
-
Fast Generation of Irredundant Sum-Of-Products Forms from Binary Decision Diagrams
-
S. Minato. Fast Generation of Irredundant Sum-Of-Products Forms from Binary Decision Diagrams. In Proc. SASIMI'92.
-
Proc. SASIMI'92
-
-
Minato, S.1
-
11
-
-
33846545005
-
DAG-aware AIG rewriting: A fresh look at combinational logic synthesis
-
A. Mishchenko, S. Chatterjee, and R. Brayton. DAG-aware AIG rewriting: A fresh look at combinational logic synthesis. In Proc. DAC'06, pages 532-536, 2006.
-
(2006)
Proc. DAC'06
, pp. 532-536
-
-
Mishchenko, A.1
Chatterjee, S.2
Brayton, R.3
-
12
-
-
33846589332
-
-
February
-
A. Mishchenko, S. Chatterjee, and R. Brayton. Improvements to Technology Mapping for LUT-based FPGAs. volume 26:2, pages 240-253, February 2007.
-
(2007)
Improvements to Technology Mapping for LUT-based FPGAs
, vol.26
, Issue.2
, pp. 240-253
-
-
Mishchenko, A.1
Chatterjee, S.2
Brayton, R.3
-
15
-
-
2442557232
-
Efficient Translation of Boolean Formulas to CNF in Formal Verification of Microprocessors
-
M. N. Velev. Efficient Translation of Boolean Formulas to CNF in Formal Verification of Microprocessors. Proc. of Conf. on Asia South Pacific Design Aut. (ASP-DAC), 2004.
-
(2004)
Proc. of Conf. on Asia South Pacific Design Aut. (ASP-DAC)
-
-
Velev, M.N.1
-
16
-
-
26444545052
-
Benchmarking SAT Solvers for Bounded Model Checking
-
Proc. SAT'05, number in, Springer-Verlag
-
E. Zarpas. Benchmarking SAT Solvers for Bounded Model Checking. In Proc. SAT'05, number 3569 in LNCS. Springer-Verlag, 2005.
-
(2005)
LNCS
, vol.3569
-
-
Zarpas, E.1
|