DRIE from MEMS to wafer-level packaging

Solid State Technology

Volumn 50, Issue 12, 2007, Pages 58-60

  Lea, Leslie M ^a   Short, Carolyn L ^a  

^a Surface Technology Systems plc   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; DIGITAL INTEGRATED CIRCUITS; PLASMA ETCHING; REACTIVE ION ETCHING; SIZE DETERMINATION;

PLASMA ETCH TOOLS; STACKED DIES;

MEMS;

EID: 38049123027     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (7)

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3. J.H. Wu, J. Schlovin, J.A. del Alamo, "A Through-wafer Interconnect in Silicon for RFICs," IEEE Trans. on Electron Devices, Vol. 51, No. 11, Nov. 2004.
4. C-J Lin, M-T Lin, S-P Wu, F-G Tseng, "High Density and Through-wafer Copper Interconnects and Solder Bumps for MEMS Wafer-level Packaging," Jour. of Microsystem Technologies, Vol. 10, No. 6-7, Oct. 2004.
5. J.K. Bhardwaj, H. Ashraf, "Advanced Silicon Etching Using High-density Plasmas," Proc. SPIE, 2639, 224, 1995.
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7. S.A. McAuley, H. Ashraf, L. Atabo, A. Chambers, S. Hall, J. Hopkins, G.J. Nicholls, "Silicon Micromachining Using a High-density Plasma Source," Phys. D. Appl. Phys., 34, pp. 2769-2774, 2001.